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CUSAT B.Tech S5 CS Solved Question for Microprocessor Based System Design

CUSAT B.Tech S5 CS Solved Question for Microprocessor Based System Design June-2011

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ANSWERS

CUSAT B.Tech S5 CS Solved Question for Microprocessor Based System Design June-2011

PART A

 

  1. a) Explain memory segmentation and segment registers of 8086.

The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is generated using segment and offset registers each of the size 16-bit.The content of a segment register also called as segment address, and content of an offset register also called as offset address. To get total physical address, put the lower nibble 0H to segment address and add offset address.

 Segment registers:

To complete 1Mbyte memory is divided into 16 logical segments. The complete 1Mbyte memory segmentation is as shown in fig 1.5. Each segment contains 64Kbyte of memory. There are four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory, which is used to store stack data.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. It points to the data segment memory where the data is resided.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment which essentially is another data segment of the memory. It also contains data.

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  1. b)   What you mean by Assembler Directives?Explain with examples.

Types of hints are given to the assembler using some predefined alphabetical strings called assembler directives. Assembler directives help the assembler to correctly understand the

assembly language programs to prepare the codes.The logical errors or other programming errors are not found out by the assembler. For completing all these tasks, an assembler needs some hints from the programmer, i.e. the required storage for a particular constant or a variable, logical names of the segments, types of the different routines and modules, end of file, etc.

DB: Define Byte The DB directive is used to reserve byte or bytes of memory locations in the available memory.

Example:

LIST DB 0lH, 02H, 03H, 04H

This statement directs the assembler to reserve four memory locations for a list named LIST and initialise them with the above specified four values.

DW: Define Word. The DW directive serves the same purposes as the DB directive, but it now makes the assembler reserve the number of memory words (16-bit) instead of bytes. Some examples are given to explain this directive.

Examples

WORDS DW 1234H, 4567H, 78ABH, 045CH

ASSUME: Assume Logical Segment Name The ASSUME directive is used to inform the assemble, the names of the logical segments to be assumed for different segments used in the program. In the assembly language program, each segment is given a name. For example, the code segment may be given the name CODE, data segment may be given the name DATA etc.

  1. c) Compare the minimum mode and maximum mode operations of 8086

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its MN/MX* pin to logic1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic may be required for selecting memory or I/O devices, depending upon the address map of the system. The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086. Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signal. They are controlled by two signals, namely, DEN* and DT/R*. The DEN* signal indicates that the valid data is available on the data bus, while DT/R indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROMS are used for monitor storage, while RAMs for users program storage. A system may contain I/O devices for communication with the processor as well as some special purpose I/O devices. The clock generator generates the clock from the crystl oscillator and then shapes it and divides to make it more precise so that it can be used as an accurate timing reference for the system. The clock generator also synchronizes some external signals with the system clock

In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus controller derives the control signals using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The other components in the system are the same as in the minimum mode system The basic functions of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information made available by the processor on the status lines. The bus controller chip has input lines S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It derives the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*. The AEN*, IOB and CEN pins are specially useful for multiprocessor systems. AEN* and IOB are generally grounded.

   

  1. d) Compare 8086 processor with 8088.

8086

  • It has 16 data lines and 20 address lines
  • It has 6 byte instruction queue.
  • It has BHE to acces higher byte
  • M/IO is used for memoy or IO access
  • Comparitively less time for excecution

8088

  • It has 8 data lines and 20 address lines
  • A 4 byte instruction queue is used due to 8 bit bus instruction fetching is slow and 4 byte are sufficient for queue.
  • As data bus is 8 bit wide It does not have BHE pin.The pin SS0is used instead of BHE in min mode.The pin SS0 is logically equivalent to S0 in max mode
  • IO/M is used for memoy and IO access
  • Comparitively less time for excecuti
  1. e)   Explain the DMA transfer and operation of 8086.

The Direct Memory Access or DMA mode of data transfer is the fastest amongst

all the modes of data transfer. In this mode, the device may transfer data directly to/from

memory without any interference from the CPU. The device requests the CPU (through a

DMA controller) to hold its data, address and control bus, so that the device may transfer

data directly to/from memory.

The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

Intel’s 8257 is a four channel DMA controller designed to be interfaced with their family

of microprocessors. The 8257, on behalf of the devices, requests the CPU for bus access

using local bus request input i.e. HOLD in minimum mode. In maximum mode of the

microprocessor RQ/GT pin is used as bus request input.

On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in maximum

mode) from the CPU, the requesting devices gets the access of the bus, and it completes

the required number of DMA cycles for the data transfer and then hands over the control

of the bus back to the CPU. The 8257 performs the DMA operation over four independent DMA channels. Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and terminal count register There are two common registers for all the channels, namely, mode set register and status register. Thus there are a total of ten registers. The CPU selects one of these ten registers using address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting one of these registers.

 

 

 

DMA Address Register

Each DMA channel has one DMA address register. The function of this register is to store the address of the starting memory location, which will be accessed by the DMAchannel. Thus the starting address of the memory block which will be accessed by the device is first loaded in the DMA address register of the channel.

Terminal Count Register

Each of the four DMA channels of 8257 has one terminal count register (TC).

This 16-bit register isused for ascertaining that the data transfer through a DMA channel

ceases or stops after the required number of DMA cycles. The low order 14-bits of the terminal count register are initialised with the binary equivalent of the number of required DMA cycles minus one.

Mode Set Register

The mode set register is used for programming the 8257 as per the requirements of the system. The function of the mode set register is to enable the DMA channels individually and also to set the various modes of operation.

Status Register

The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the terminal count status for the four individual channels. If any of these bits is set, it indicates that the specific channel has reached the terminal count condition.

  f)Explain the paging mechanism of 80386.

Paging

  • PAGING OPERATION: Paging is one of the memory management techniques used for virtual memory multitasking operating system.
  • The segmentation scheme may divide the physical memory into a variable size segments but the paging divides the memory into a fixed size pages.
  • The segments are supposed to be the logical segments of the program, but the pages do not have any logical relation with the program.
  • The pages are just fixed size portions of the program module or data.
  • The advantage of paging scheme is that the complete segment of a task need not be in the physical memory at any time.
  • Only a few pages of the segments, which are required currently for the execution need to be available in the physical memory. Thus the memory requirement of the task is substantially reduced, relinquishing the available memory for other tasks.
  • Whenever the other pages of task are required for execution, they may be fetched from the secondary storage.
  • The previous page which are executed, need not be available in the memory, and hence the space occupied by them may be relinquished for other tasks.
  • Thus paging mechanism provides an effective technique to manage the physical memory for multitasking systems.

Paging Unit: The paging unit of 80386 uses a two level table mechanism to convert a linear address provided by segmentation unit into physical addresses.

  • The paging unit converts the complete map of a task into pages, each of size 4K. The task is further handled in terms of its page, rather than segments.
  • The paging unit handles every task in terms of three components namely page directory, page tables and page itself.

 g)Expalain the salient featuers of Pentium family processors.

  1. h) Compare a microcontroller with a microprocessor.

Microprocessor

  • No extra peripherals
  • Accessing time is very high
  • Maximum number of data transfer instructions
  • Instructions for bitwise operation is less
  • Less reliable
  • Can act as a microcomputer by adding external devices
  • Only one or two pins performs multiple functions.

Microcontroller

  • extra peripherals needed
  • Accessing time is low
  • Less number of data transfer  instructions
  • Instructions for bitwise operation is more
  • More reliable
  • Without adding any extra peripherals it can act as a microcomputer
  • More than two pins performs multiple functions.

 

 

CUSAT B.Tech S5 CS Solved Question for Microprocessor Based System Design June-2011- PART B

 

II.With neat block diagram,Explain the internal architecture of intel 8086 microprocessor,Also explain the various registers of 8086.(15)

The internal architecture 8086 microprocessor is as shown in the fig 1.2.The 8086 CPU is divided into two independent functional parts, the Bus interface unit (BIU) and execution unit (EU). The Bus Interface Unit contains Bus Interface Logic, Segment registers, Memory

addressing logic and a Six byte instruction object code queue. The execution unit contains the Data and Address registers, the Arithmetic and Logic Unit, the Control Unit and flags.

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The BIU sends out address, fetches the instructions from memory, read data from ports and memory, and writes the data to ports and memory. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit.The execution unit (EU) of the 8086 tells the BIU where to fetch instructions or data from, decodes instructions and executes instruction. The EU contains control circuitry which directs internal operations. A decoder in the EU translates instructions fetched from memory into a series of actions which the EU carries out. The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment, decrement,

complement or shift binary numbers. The EU is decoding an instruction or executing an instruction which does not require use of the buses.

The Queue: The BIU fetches up to 6 instruction bytes for the following instructions. The BIU stores these prefetched bytes in first-in-first-out register set called a queue. When the EU is ready for its next instruction it simply reads the instruction byte(s) for the instruction from the queue in the BIU. This is much faster than sending out an address to the system memory and waiting for memory to send back the next instruction byte or bytes. Except in the case of JMP and CALL instructions, where the queue must be dumped and then reloaded starting from a new address, this prefetch-and-queue scheme greatly speeds up processing. Fetching the next instruction while the current instruction executes is called pipelining.

Physical address formation:

The 8086 addresses a segmented memory. The complete physical address which is 20-bits long is generated using segment and offset registers each of the size 16-bit.The content of a segment register also called as segment address, and content of an offset register also called as offset address. To get total physical address, put the lower nibble 0H to segment address and add offset address. The fig 1.3 shows formation of 20-bit physical address

Register organization of 8086:

8086 has a powerful set of registers containing general purpose and special purpose registers. All the registers of 8086 are 16-bit registers. The general purpose registers, can be used either 8-bit registers or 16-bit registers. The general purpose registers are either used for holding the data, variables and intermediate results temporarily or for other purpose like counter or for storing offset address for some particular addressing modes etc. The special purpose registers are used as segment registers, pointers, index registers or as offset storage registers for particular addressing

modes. Fig 1.4 shows register organization of 8086. We will categorize the register set into four groups as follows:

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General data registers:

The registers AX, BX, CX, and DX are the general 16-bit registers.

AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations, rotate and string manipulation.

BX Register: This register is mainly used as a base register. It holds the starting base location of a memory region within a data segment. It is used as offset storage for forming physical address in case of certain addressing mode.

CX Register: It is used as default counter or count register in case of string and loop instructions.

DX Register: Data register can be used as a port number in I/O operations and implicit operand or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

Segment registers:

To complete 1Mbyte memory is divided into 16 logical segments. The complete 1Mbyte memory segmentation is as shown in fig 1.5. Each segment contains 64Kbyte of memory. There are four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly.The CS register is automatically updated during far jump, far call and far return instructions. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction. It is used for addressing stack segment of memory. The stack segment is that segment of memory, which is used to store stack data.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions. It points to the data segment memory where the data is resided.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It also refers to segment which essentially is another data segment of the memory. It also contains data.

Pointers and index registers.

The pointers contain within the particular segments. The pointers IP, BP, SP usually contain offsets within the code, data and stack segments respectively

Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data addresses in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

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Flags Register determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program.The 8086 flag register as shown in the fig 1.6. 8086 has 9 active flags and they are divided into two categories:

  1. Conditional Flags
  2. Control Flags

Conditional Flags

Conditional flags are as follows:

Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from

lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given

by D3 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the  processor to perform binary to BCD conversion.

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Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.

Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the result of operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the execution unit.

Control flags are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a program at a time for debugging. When trap flag is set, program can be run in single step mode.

Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be cleared by executing CLI instruction.

Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from higher memory address to lower memory address. When it is reset, the string bytes are accessed from lower memory address to higher memory address.

 

 

 

III        a)         Explain the following instructions of 8086(5)

  1. SCASB

SCASB No operands Compare bytes: AL from ES:[DI].    

  1. CWD

Convert Word to Double word.

Example:

CWD         ; DX AX = 0FFFFh:0FFFBh

 

  • SAHF           

SAHF No operands Store AH register into low 8 bits of Flags register.

  1. LEA

memory Load Effective Address LEA AX, m

  1.         AAA

ASCII Adjust after Addition.
Corrects result in AH and AL after addition when working with BCD values.                        MOV AX, 15   ; AH = 00, AL = 0Fh                                                             AAA          ; AH = 01, AL = 05

 

  1. b) Write an assembly language programme to reverse a string store in a memory location (10)

DATA SEGMENT
STR1 DB “MAHESH$”
STR2 DB 7 DUP (‘$’)
MSG1 DB 10,13,’STORED STRING IN MEMORY IS : $’
MSG2 DB 10,13,’REVERSE STRING IS : $’
DATA ENDS

DISPLAY MACRO MSG
MOV AH,9
LEA DX,MSG
INT 21H
ENDM
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START:
MOV AX,DATA
MOV DS,AX

DISPLAY MSG1

DISPLAY STR1

LEA SI,STR2
LEA DI,STR1
ADD DI,5

MOV CX,6
REVERSE:
MOV AL,[DI] MOV [SI],AL
INC SI
DEC DI
LOOP REVERSE

DISPLAY MSG2

DISPLAY STR2

MOV AH,4CH
INT 21H
CODE ENDS
END START

 

  1. Draw a neat block diagram of 8259 and explain its features.(15)

PROGRAMMABLE INTERRUPT CONTROLLER 8259A

a programmable interrupt controller which is able to handle a number of interrupts at a time. This controller takes care of a number of simultaneously appearing interrupt requests along with their types and priorities. This will relieve the processor from all these tasks. The programmable interrupt controller 8259A from Intel is one such device. The predecessor 8259 was designed to

operate only with 8-bit processors like 8085. A modified version, 8259A was later introduced that is compatible with 8-bit as well as 16-bit processors.

Architecture of 8259A

The architectural block diagram of 8259A is shown in Fig. 1.1

Interrupt Request Register (IRR) The interrupts at IRQ input lines are handled by Interrupt Request Register internally. IRR stores all the interrupt requests in it in order to serve them one by one on the priority basis.

In-Service Register (ISR) This stores all the interrupt requests those are being served, i.e ISR keeps a track of the requests being served.

Priority Resolver This unit determines the priorities of the interrupt requests appearing simultaneously. The highest priority is selected and stored into the corresponding bit of ISR during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in fixed priority mode. The priorities however may be altered by programming the 8259A in

rotating priority mode.

Interrupt Mask Register (IMR) This register stores the bits required to mask the interrupt puts. IMR operates on IRR at the direction of the Priority Resolver.

Interrupt Control Logic This block manages the interrupt and interrupt acknowledge signals to be sent to the CPU for serving one of the eight interrupt requests. This also accepts interrupt acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the data bus.

Data Bus Buffer This tristate bidirectional buffer interfaces internal 8259A bus to the microprocessor system data bus. Control words, status and vector information pass through buffer during read or write operations.

Read write Control Logic This circuit accepts and decodes commands from the CPU. This also allows the status of the 8259A to be transferred on to the data bus.

Cascade Buffer/Comparator This block stores and compares the ID’s of all the 8259As used in the system. The three I/O pins CAS0-2 are outputs

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Fig1.1. 8259A Block Diagram

when the 8259A is used as a master. The same pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of the interrupting slave device on these lines. The slave thus selected, will send its pre programmed vector address on the data bus during the next INTA pulse.

  1. Explain about the microprocessor interconnection topologies used in interfacing processors(15)
  2. a) Explain the difference between RISC and CISC processors.(10)

RISC

  • Fewer number of instructions.
  • Same length instructions
  • One clock cycle is needed for executing instructions
  • Large number of general purpose Registers
  • Fewer number of addressing modes
  • Pipelining is used
  • LOAD and STORE instructions are used for all memory operations

 

CISC

  • Different length instructions.so multiple clock cycle is needed
  • Large amount of instructions
  • Small number of general purpose registers
  • Large number of addressing modes
  • CISC is used to enhance development of compiler
  • It contain built in functions for complex calculations
  1. b) Explain the instruction and data caches in Pentium processors(5)
  • Both caches are organized as 2-way set associative caches with 128 sets (total 256 entries)
  • There are 32 bytes in a line (8K/256)

An LRU algorithm is used to select victims in each cache. The data cache has two ports, one for each of the two pipes. The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache,  responsible for getting raw instructions into the execution units of the Pentium processor. Instructions are fetched from the code cache or from the external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache.

 

VII.     Explain the role of segment descriptor register and tables in 80386 microprocessor.(15)

Segment Descriptor Registers: This registers are not available for programmers, rather they are internally used to store the descriptor information, like attributes, limit and base addresses of segments. The six segment registers have corresponding six 73 bit descriptor registers. Each of them contains 32 bit base address, 32 bit base limit and 9 bit attributes. These are automatically loaded when the corresponding segments are loaded with selectors

The segment descriptor provides the processor with the data it needs to map a logical address into a linear address. Descriptors are created by compilers, linkers, loaders, or the operating system, not by applications programmers.  Segment-descriptor fields are:

BASE: Defines the location of the segment within the 4 gigabyte linear address space. The processor concatenates the three fragments of the base address to form a single 32-bit value.

LIMIT: Defines the size of the segment. When the processor concatenates the two parts of the limit field, a 20-bit value results. The processor interprets the limit field in one of two ways, depending on the setting of the granularity bit:

  1. In units of one byte, to define a limit of up to 1 megabyte.
  2. In units of 4 Kilobytes, to define a limit of up to 4 gigabytes. The limit is shifted left by 12 bits when loaded, and low-order one-bits are inserted.

Granularity bit: Specifies the units with which the LIMIT field is interpreted. When thebit is clear, the limit is interpreted in units of one byte; when set, the limit is interpreted in units of 4 Kilobytes.

TYPE: Distinguishes between various kinds of descriptors.

DPL (Descriptor Privilege Level): Used by the protection mechanism

Segment-Present bit: If this bit is zero, the descriptor is not valid for use in address transformation; the processor will signal an exception when a selector for the descriptor is loaded into a segment register. The operating system is free to use the locations marked AVAILABLE. Operating systems that implement segment-based virtual memory clear the present bit in either of these cases:

  • When the linear space spanned by the segment is not mapped by the paging mechanism.
  • When the segment is not present in memory.

Accessed bit: The processor sets this bit when the segment is accessed; i.e., a selector for the descriptor is loaded into a segment register or used by a selector test instruction. Operating systems that implement virtual memory at the segment level may, by periodically testing and clearing this bit, monitor frequency of segment usage.

Creation and maintenance of descriptors is the responsibility of systems software, usually requiring the cooperation of compilers, program loaders or system builders, and therating system.

DESCRIPTOR TABLES: These descriptor tables and registers are manipulated by the operating system to ensure the correct operation of the processor, and hence the correct execution of the program. • Three types of the 80386 descriptor tables are listed as follows:

  • GLOBAL DESCRIPTOR TABLE ( GDT )
  • LOCAL DESCRIPTOR TABLE ( LDT )
  • INTERRUPT DESCRIPTOR TABLE ( IDT )

DESCRIPTORS: The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptor of 80386 are 8-byte quantities access right or attribute bits along with the base and limit of the segments.

  • Descriptor Attribute Bits: The A (accessed) attributed bit indicates whether the segment has been accessed by the CPU or not.
  • The TYPE field decides the descriptor type and hence the segment type.
  • The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor ( S=1).

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The DPL field specifies the descriptor privilege level.

  • The D bit specifies the code segment operation size. If D=1,the segment is a 32-bit operand segment, else, it is a 16-bit operand segment.
  • The P bit (present) signifies whether the segment is present in the physical memory or not. If P=1, the segment is present inthe physical memory.
  • The G (granularity) bit indicates whether the segment is page addressable. The zero bit must remain zero for compatibility with future process. The AVL (available) field specifies whether the descriptor is for user or for operating system.
  • The 80386 has five types of descriptors listed as follows:
  1. Code or Data Segment Descriptors.
  2. System Descriptors.
  3. Local descriptors.
  4. TSS (Task State Segment) Descriptors.
  5. GATE Descriptors.
  • The 80386 provides a four level protection mechanism exactly in the same way as the 80286 does.

VIII.    Explain the architecture of 8051 with necessary diagrams(15)

The block diagram of 8051 shows all the features unique to Microcontroller.

  • Internal ROM & RAM
  • Input &output ports with programmable pins
  • Timer and Counter
  • Serial data Communication

The 8051 architecture consists of these specific features 8-bit CPU with Register A and B 16-bit program counter (PC) and data pointer (DPTR) 8 bit program status word (PSW) Internal ROM or EPROM Internal RAM 128 bytes In this 4 Register banks, each containing 8 registers 16 bytes which may be addressed at bit level 8 bytes of general purpose data memory

  • 32 input /output pins arranged as 4-8 bit ports P0-P3
  • Two 16 bit timer/counters (TO-T1)
  • Fully duplexed serial data receiver/transmitter (SBUF)
  • Control register TMOD, TCON, SCOM, PCON, IP and IE

Oscillator and Clock circuit

8051 oscillator and Clocks Pins XTAL1 and XLAT2 are provided for connecting resonant network to form an oscillator. The methods used in these networks are:  Ceramic resonators  Quartz crystal and capacitor.

PROGRAM COUNTER

Program instruction bytes are fetched from locations in memory that are present at address given by the PC. The PC is automatically incremented after every instruction byte is fetched. The PC is the only register that does not have an internal address.

DPTR

This register is made up of two 8-bit registers, named DPH and DPL, which are used to furnish memory addresses for internal and external code access and external data access.

A and B CPU Registers: The A (accumulator) register is the most versatile of the two CPU registers and is used for many operations. The A register is also used for all data transfers between the 8051 and any external memory. The B register is used with the A register for multiplication and division operations.

The Stack and the Stack Pointer . The 8-bit Stack pointer (SP) register is used by the 8051 to hold an internal RAM address that is called the top of the stack. The address held in the SP register is the location in internal RAM where the last byte of data was stored by a stack operation.

Counters & Timers Consist of two 16 bit Counters named T0 and T1 are provided for general use of the programmer. Each may be programmed to count internal clock pulses, acting as a timer or programmed to count external pulse as a counter. The Counter are divided into two 8 byte register called the timer low (TL0,TL1) and high (TH,TH1) bytes. All counter action is controlled by bit state in the timer mode control register TMOD, the timer/counter control register (TCON) and certain program instruction. TMOD – controls 2 timers with each 4 bit controlling one Timer. TCON – has control bits and flags for timer in upper nibble and control bit and flags for external interrupts in the lower nibble.

Timer mode of operation There are four modes of operation specific mode is selected using bit M1 & M0 in TMOD register

TIMER mode 0 TMOD register set to 00B, resulting in initializing THX register as 8-bit counter and TLX as a five bit counter. The pulse input is divided by 32D in TL so that TH counts the original oscillator frequency reduced by a total of 384D.

Timer mode 1 Differs by Mode 0 as TLX is configured as a full 8-bit counter. When mode bit are set to 01B in TMOD.

Timer mode 2 TMOD register is set to 10B resulting to use only the TLX counter as a 8-bit counter. THX is used to hold a value that is loaded into TLX every time, TLX overflow from FFH to 00H. The timer flag is also set when TLX overflows.

Timer mode 3 In this both the Timers 0 and 1cannot set to mode 3., because placing timer1 in MODE 3 causes it to stop counting. The control bit TRI and timer 1 flag TFI are used by timer 0.

Serial data input/output Computers must be able to communicate with other computers in modern multiprocessor distributed system. One cost-effective way to communicate is to send and receive data bits serially.

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Port 0 pins may serve as inputs, outputs or when used together as a bidirectional low-order address and data bus for external memory

Port 1 pins have no dual functions therefore the output latch is connected directly to the gate of the lower FET, which has an FET circuit labeled internal FET pull up as an active pull up load

Port 2 may be used as an input/output port similar in operation to port 1 the alternate use of port 2 is to supply a high-order address byte in conjunction with the port 0 low-order byte to address external memory.

Port 3 is an input/output port similar to port 1. The input and output functions can be programmed under the control of the P3 latches or under the control of various other specific function registers.

 

  1. Explain the memory organization of 8051 with necessary diagrams(15)

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The 8051 has two types of memory and these are Program Memory and Data Memory. Program Memory (ROM) is used to permanently save the program being executed, while Data Memory (RAM) is used for temporarily storing data and intermediate results created and used during the operation of the microcontroller. Depending on the model in use (we are still talking about the 8051 microcontroller family in general) at most a few Kb of ROM and 128 or 256 bytes of RAM is used. However…

All 8051 microcontrollers have a 16-bit addressing bus and are capable of addressing 64 kb memory. It is neither a mistake nor a big ambition of engineers who were working on basic core development. It is a matter of smart memory organization which makes these microcontrollers a real “programmers’ goody“.

Program Memory

The first models of the 8051 microcontroller family did not have internal program memory. It was added as an external separate chip. These models are recognizable by their label beginning with 803 (for example 8031 or 8032). All later models have a few Kbyte ROM embedded. Even though such an amount of memory is sufficient for writing most of the programs, there are situations when it is necessary to use additional memory as well. A typical example are so called lookup tables. They are used in cases when equations describing some processes are too complicated or when there is no time for solving them. In such cases all necessary estimates and approximates are executed in advance and the final results are put in the tables (similar to logarithmic tables).

Data Memory

Data Memory is used for temporarily storing data and intermediate results created and used during the operation of the microcontroller. Besides, RAM memory built in the 8051 family includes many registers such as hardware counters and timers, input/output ports, serial data buffers etc. The previous models had 256 RAM locations, while for the later models this number was incremented by additional 128 registers. However, the first 256 memory locations (addresses 0-FFh) are the heart of memory common to all the models belonging to the 8051 family. Locations available to the user occupy memory space with addresses 0-7Fh, i.e. first 128 registers. This part of RAM is divided in several blocks.

The first block consists of 4 banks each including 8 registers denoted by R0-R7. Prior to accessing any of these registers, it is necessary to select the bank containing it. The next memory block (address 20h-2Fh) is bit- addressable, which means that each bit has its own address (0-7Fh). Since there are 16 such registers, this block contains in total of 128 bits with separate addresses (address of bit 0 of the 20h byte is 0, while address of bit 7 of the 2Fh byte is 7Fh). The third group of registers occupy addresses 2Fh-7Fh, i.e. 80 locations, and does not have any special functions or features.

Additional RAM

In order to satisfy the programmers’ constant hunger for Data Memory, the manufacturers decided to embed an additional memory block of 128 locations into the latest versions of the 8051 microcontrollers. However, it’s not as simple as it seems to be… The problem is that electronics performing addressing has 1 byte (8 bits) on disposal and is capable of reaching only the first 256 locations, therefore. In order to keep already existing 8-bit architecture and compatibility with other existing models a small trick was done.

It means that additional memory block shares the same addresses with locations intended for the SFRs (80h- FFh). In order to differentiate between these two physically separated memory spaces, different ways of addressing are used. The SFRs memory locations are accessed by direct addressing, while additional RAM memory locations are accessed by indirect addressing.

 

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