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# KTU B.TECH S3 MODEL QUESTIONS-Switching Theory & Logic Design

## KTU B.TECH S3 MODEL QUESTIONS Switching Theory & Logic Design

THIRD SEMESTER B.TECH  DEGREE EXAMINATION  DECEMBER 2016

CS 203: Switching Theory and Logic Design

Time: 3 Hrs                                                                                                                 Marks: 100

PART A

( Answer All Questions Each carries 3 Marks )

1.     Perform the following conversions

i)6A to Octal

ii)(673.62)8 to decimal

(793.75)10 to Hexa decimal

1. What you mean by weighted code?
2. Add the following BCD numbers.

01100111 + 01010011 .

1. What are the universal gates? Why they are called universal gate?

PART B

( Answer any TWO, Each carries 9 Marks )

1. Simplify the following expresstions using karnaugh map and NAND gate.

a)                                                                                                                                                               (7  marks)

b)                                                                                                                                                                                            (2 mark)

1. Minimize the following function F(A,B,C,D)= Σm(6,7,8,9) assuming that the condition having both A=1 and B= 1 ( don’t care condition = Σm(12,13,14,15)) can never occur. Realize the digital circuit using

i)NAND gate

ii)NOR gates

1. Minimize the function F= Σm(4,5,10,11,15,1820,24,26,30,31) + Σm(9,12, 14,16,19,21,25) where Σ are the minters corresponding to don’t care conditions using QuinMcClusky method

PART C

( Answer All Questions Each Carries 3 Marks )

1. Explain binary subtractor.
2. show the logic digram of R-S flipflop with four NAND gate
3. what are the differences of flip-flop and Latch?
4. Implement 4:1 multiplexer

PART D

( Answer any TWO, Each carries 9 Marks )

1. Explain how a look ahead adder speeds up the addition process.(9 marks)
2. a) Expand  to min terms and max terms      (4 marks)

b) Describe the differences between PLA and PAL(5 mark)

14.a)Implement Full adder circuit using NAND gate only.(5 marks)

b) Use a multiplexer to implement the function                                                                                                                             (4 marks)

PART E

( Answer any FOUR, Each carries 10 Marks )

1. (a) Design a 4 but binary ripple counter using flip-flop that trigger on the

i) Positive edge transition

ii) Negative edge transition (10)

1. Draw a synchronous sequential circuit using D flip-flop for the state diagram in

.

1. a) Design a mod 6 asynchronous up counter using T flip-flop(6 marks)
2. b) Differentiate between combinational and sequential circuits (4 marks)
3. Design BDC counter using JK flip-flop
4. Draw and explain 4 bit Johnson counter. Draw the timing diagram also.

a) what is race condition? How it can be avoided?(5 marks)

b) Design T flip –flop using JK flip-flop.(5 marks)

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### Switching Theory & Logic Design

KTU B.TECH S3  MODEL QUESTIONS   Switching Theory & Logic Design

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